The present invention relates to a semiconductor memory device; and, more particularly, to the semiconductor memory device for providing a bit line sense amplifier which can support an over driving operation during a data access.
As generally known, data stored in memory cells of a DRAM is amplified to be read by bit line sense amplifiers. At initial enable period of the bit line sense amplifiers, a DRAM performs an operation to supply increased supply voltage to the bit line sense amplifiers, which is called the over driving operation.
FIG. 1 illustrates a signal timing diagram explaining an operation of a conventional semiconductor memory device. When a selected word line WL in the memory cell is activated, the data, i.e., charges, stored in the memory cell are transmitted to a bit line pair. Accordingly, the bit line BL and a bit line bar BLB have a fine voltage potential deference dV, which occurs in a period 102.
Thereafter, a bit line sense amplifier is enabled and voltage levels of the bit line BL and the bit line bar BLB are boosted up into a core voltage VCORE and a ground voltage VSS respectively. Driving supply lines of the bit line sense amplifier are supplied with supply voltages for enabling the bit line sense amplifier. The first driving supply line (RTO line) is supplied with the core voltage and the second driving supply line (SB line) is supplied with the ground voltage VSS.
At the initial enable period of the bit line sense amplifier, the RTO line is supplied with higher voltage than the core voltage VCORE for the over driving operation. The over driving period 103 described in FIG. 1 is determined according to the width of an over driving pulse.
FIG. 2 illustrates a schematic circuit diagram showing a conventional over driving pulse generator, and FIG. 3 illustrates a signal timing diagram depicting an operation of the conventional over driving pulse generator.
The conventional over driving pulse generator includes a delay unit 201, a NAND gate 202 and an inverter 203. The delay unit 201 is provided with odd number of inverters in series to delay an input signal 211. The NAND gate 202 receives the input signal 211 and an output of the delay unit 201. The inverter 203, inverting an output of the NAND gate 202, outputs over driving pulse ODP.
The input signal 211 on a node A is activated in response to an active command and is inactivated in response to a precharge command. The input signal 211 is a signal delayed until operation of the bit line sense amplifier after the active command is input. When the input signal 211 is input to the node A, a delayed signal 212 is generated by the delay unit 201. The NAND gate 202 and the inverter 203 perform a logic operation to the input signal 211 and the delayed signal 212. The conventional over driving pulse generator generates the over driving pulse ODP having activation period by a delay time of the delay unit 201. The width of the over driving pulse ODP is determined according to the predetermined delay time.
As the width of the over driving pulse ODP is wide when a supply voltage VDD is a high level, the level of the core voltage VCORE is increased. A discharge operation which compares the core voltage VCORE with a reference voltage and discharges the core voltage VCORE according to the comparison result is required in order to decrease the core voltage VCORE. Unnecessary power is consumed.
In addition, because a bit line precharge voltage VBLP is generated based on the core voltage VCORE, the level of the bit line precharge voltage VBLP is also increased. Due to the increased bit line precharge voltage, the voltage potential difference dV between the bit line BL and a bit line bar BLB is changed. When sensing a logic high level of data transmitted to the bit line pair from the memory cell, malfunction may be caused.
In case when the supply voltage VDD is a low level, for example, the supply voltage VDD is a 1.8 voltage level and the core voltage VCORE is a 1.6 voltage level in DDR2 SDRAM, a power for increasing the core voltage VCORE is insufficiently supplied if the over driving pulse ODP has a short pulse width. The power consumed represents the lack of the core voltage VCORE. If active commands are subsequently input before the core voltage VCORE is recovered, malfunctions or character deterioration of parameters such as tRCD can be caused.